
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity hysteris is
    Port ( clk : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           in_voltage_high : in  STD_LOGIC;
           in_voltage_low : in  STD_LOGIC;
           out_battery : out  STD_LOGIC;
           out_capacitor : out  STD_LOGIC);
end hysteris;

architecture Behavioral of hysteris is

	type energy_state is (RESET_STATE, BATTERY_STATE, CAPACITOR_STATE);
   signal state, newstate: energy_state;
   
begin
    process (clk)
      begin
        if (rising_edge (clk)) then
            if (reset = '1') then
                state <= RESET_STATE;
            else
                state <= newstate;
            end if;
        end if;
    end process;
    
  lblstate: process(state, in_voltage_high, in_voltage_low, clk, reset)
  begin
  case state is 
    when RESET_STATE =>
		out_battery <= '0';
		out_capacitor <= '1';

      if (in_voltage_low = '1') then
        newstate <= CAPACITOR_STATE;
		else
		  newstate <= BATTERY_STATE;
      end if;
		
	 when CAPACITOR_STATE =>
		out_battery <= '1';
		out_capacitor <= '0';

      if (in_voltage_low = '0') then
        newstate <= BATTERY_STATE;
		else
		  newstate <= CAPACITOR_STATE;
      end if;
		
	 when BATTERY_STATE =>
		out_battery <= '0';
		out_capacitor <= '1';

      if (in_voltage_high = '1') then
        newstate <= CAPACITOR_STATE;
		else
		  newstate <= BATTERY_STATE;
      end if;
  end case;
  end process;

end Behavioral;

